>You're correct. I was assuming that you had continuous access to the sine wave. That would be too easy. >I guess it's safe to assume then that the `off-chip electronics' do some kind of >conditioning to guard against the noise problems I alluded to before. I haven't I would hope so. They haven't finished a spec yet, but that's an item I can write in. >variation], otherwise there will be jitter if N doesn't exactly divide into >period of the sine wave). My plan was to accumulate the error and every M steps insert/delete a uS or so. My goal is to hit 0V within 6 uS of the mains. >What does the synthesized sine wave need to lock to? Incoming power from the electric company 3-phase setup. I will only use one phase as my master reference, the other is assumed to be 90 degrees off. >Is it sufficient to generate the right frequency? Yes, but be locked to the source for phase. It's for continuous UPS equipment. I have to generate the sine waves, and lock to the incoming frequency off the mains. The frequency may change slowly but will nominally be either 50 or 60 Hz. My portion is simply to lock to the incoming wave, generate the sine waves (on a parallel DAC), and if the input goes away I just lock to the last reasonable frequency. When line power comes back on, I will need to lock to it and once locked, flip a switch to enable the mains to provide power again (mains are locked out after a failure). My other input is "phase present" for each phase of the input power. If mains are not present at startup, I default to the last nominal frequency (either 50 or 60 Hz). That is not necessarily the last frequency I saw due to the way lines go dead. The trickiest part of the whole thing will be that I will be crossing 0 at a different time the the inputs, because there is a lag time in the power electronics vs. the sine wave I am feeding them. Andy -- http://www.piclist.com hint: To leave the PICList mailto:piclist-unsubscribe-request@mitvma.mit.edu