At 10:01 AM 8/21/00 -0600, you wrote:
>
>Yeah, I think this is the answer. PIC and Scenix have been marketed
>as having deterministic timing, in the sense that you could know
>"exactly" how many cycles both your code and your interrupts will
>take. This is converse to the std CISC processors, where the same
>instruction can take vastly different #cycles, depending upon the
>arguments and addressing modes.

Deterministic means that it always does the same thing, under the
same conditions.

Usually code is deterministic on 8-bit processors (see below).
That is, it takes the same number of cycles every time. This *may*
not be true on some of the bigger processors because of things like
caching, multiple instruction units, speculative execution etc.
where there is more dependency on past instructions (which may have
been different because of context switches or interrupts).

Interrupts are "more" determininstic in PIC's in the sense that
when an interrupt comes at the correct time to be recognized within
the 4 clocks, it always takes the same number of clock cycles to
be recognized. CISC processors usually have to finish the
instruction in progress, which (on, say , an HC05), might be
from 2 to 11 bus cycles long (the latter for an 8 x 8 multiply), so
at 4MHz, from 1 to 5.5 usec, meaning an uncertainty for an
asynchronous interrupt of +/- 2.75usec (+/- 1.25 usec if you don't
use the MUL instruction). With the PIC, the uncertainty at 4MHz
is more like +/- 0.5usec. This is especially important if your
processor lacks a decent capture compare module, as many PICs do.
On the Scenix processor, a 3-cycle branch is aborted in progress
in order to maintain this degree of "determinism".  This, of
course, means that the total execution time (background +
interrupt) is *not* as deterministic as on an '05, but that
usually doesn't matter.

Best regards,


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