I don't know if any chips do stretch the clock. But your hardware is probably not in as bad a state as you think. You may need to add a pullup resistor, but you can get the effect of an open drain by tristating the output when you are not driving the clock. (ie: always leave the clock output latch low, and use the TRIS bit to operate the clock instead of the data bit). Bob Ammerman RAm Systems (high performance, high function, low-level software) ----- Original Message ----- From: Ian Chapman To: Sent: Thursday, July 06, 2000 7:49 AM Subject: [EE]: Do any common I2C slaves use clock stretching? > I've been successfully using "bit-banging" I2C master routines with I2C > RAMs, EEPROMs and other Philips chips without making any allowance for > the slave applying "clock stretching" (i.e. holding SCL low to give it > time to synchronise with the master). > > My assumption has been that, if the block diagram in the data sheet of a > slave device does *not* show any means of pulling SCL low (i.e. SCL is > just an input) then it cannot implement clock stretching. However, I > haven't yet found any examples of data sheets which *do* show this, so > I'm wondering whether my assumption is valid. > > Are there any common I2C slaves which *do* apply clock stretching? > > (BTW, if there are, then my hardware design has a problem as I use a > *non* open-drain PIC output to drive SCL!) > > Thanks in advance for any pointers. > -- > Ian Chapman > > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics -- http://www.piclist.com hint: The list server can filter out subtopics (like ads or off topics) for you. See http://www.piclist.com/#topics