Dan, I've done some CPLD designs for interface to PICs. In your case the
following might be of use:

   This is an SRAM Address Generator and Chip Enable Controller intended for
use with PIC16Cxx processors using Port D for a data bus and Port E for
control. It supports standard memory devices up to 512K Bytes and provides 4
auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.

Hardware Interface
==================

   Inputs:

      D0..D7: 8-Bit Data Bus
      S0..S2: 3-Bit State Select (RAM address A0-7, A8-15, A16-18 and CEx)
         /CS: Chip-Enable. Active-Low

   Outputs:

      A0..A18: 19-Bit SRAM address or general purpose latch outputs
       /CSRAM: SRAM Chip Enable. Active-Low
         /CE1: Chip Enable 1. Active-Low
         /CE2: Chip Enable 2. Active-Low
         /CE3: Chip Enable 3. Active-Low
          CE4: Chip Enable 4. Active-High

      Note: CE4 is useful for generating an LCD module Enable (E) signal as
            well as a Latch-Enable (LE) for external latches.

   Typical PIC Interface:

      RA0..RA2:  S0..S2
      RD0..RD7:  D0..D7
           RE0: /RD. External Read Data
           RE1: /WR. External Write Data
           RE2: /CS

   You might want to consider Lattice Semiconductor. Lattice provides the
ispDesignExpert software with a free 6 month license which is easy to renew.
This is an incredibly powerful free software suite. While it lacks some
features of the commercial version such as VHDL entry, this level of
capability in a `starter package' is unprecedented in the industry. It
provides schematic and ABEL-HDL entry. Also included is a gate-level
functional and timing simulator with detailed timing analysis and a waveform
viewer. There are too many features to list here. The starter software
supports their ispLSI (up to 600 Macrocells), ispGAL, MACH (formerly
Vantis), GAL, and PAL devices.

   Programming the ISP (In-System-Programming) devices is trivial with just
a 5V supply. The Lattice software to do this is free and is included in the
ispDesignExpert package or as the separate ispDownload program. The buffered
ISP download cable uses a 74HC/LS367 and a few passives and connects to a PC
parallel port. Most folks already have the parts in their `stash'.

   To build the Lattice ispDownload cable, and see some simple designs that
have been tested with a PIC, see my web page at:

      http://www.teleport.com/~thandley/Wilbure.htm

   For more information about Lattice Semiconductor's products and to
download the ispDesignExpert or ispDownload software, see:

      http://www.latticesemi.com

   - Tom


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)