Hi,

thank you for the explanations. Wrt '161 based address counters. I'd like
to remind the complete sequence PRNG with minimal feedback as address
counter. Due to the way it works it can go to 1/(2*Tprop) clock and I have
used 74A(S?)273 (I think) with clock at 66 MHz and room to spare. This is
even loadable if a hack is used (resistors to connect the stages and
tristate buffer forcing over them to load). A 16 bit counter uses 2 x 273
and 1 XOR gate + 1 inverter if I'm not wrong. There is a reset problem but
the 273 has a reset input so it's ok. I also used a 273 as a state counter
in the same project. Propagating a bit through it with all the cells
connected in series ;-). There is a neat VHDL implementation along these
lines (address counter) FYI, and there is a table of feedback points in an
appnote from Lattice or Altera I think. Of course the VHDL version is
loadable.

Peter