Tom Handley wrote:
>   Dan, I've done some CPLD designs for interface to PICs. In your case the
>following might be of use:
>
>   This is an SRAM Address Generator and Chip Enable Controller intended for
>use with PIC16Cxx processors using Port D for a data bus and Port E for
>control. It supports standard memory devices up to 512K Bytes and provides 4
>auxiliary Chip Enables. The design is implemented in a Lattice Semiconductor
>ispLSI1016E-100LJ CPLD using a 44-pin PLCC package.
>

Hi Tom, sounds like you've been there, done that already.
Can you answer:

- do you sell these chips preprogrammed?
- max count rate of your sol'n?
- chip current draw?
- cost of basic blank chip?

Thanks,
- Dan Michaels
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