Yep, the external RAM chip with a counter for address input makes a lot of
sense. I designed, but never implemented a scheme that would have the
following characteristics:

1: 12 I/O's (or maybe 11? if I recall correctly) required for access
2: easily adaptable to 2^16=64KB, 2^20=1MB, 2^24=16MB or more  bytes of RAM
maximum
3: '161 counter chips for address inputs
4: Random access time on the order of about 10-20 PIC instruction cycles.
5: Sequential read access time on the order of about 3 PIC instruction
cycles (bsf CLOCKBIT, bcf CLOCKBIT, movf DATAREG,W).
6: Sequential write access time on the order of about 5 PIC instruction
cycles (movwf DATAREG, bsf CLOCKBIT, bcf WRITEBIT, bsf WRITEBIT, bcf
CLOCKBIT)

By the way, we can kind of tie this thread to the 'PIC on Internet' thread.
A reasonable amount of SRAM, even if non-sequential access is rather
inefficient, would go a long way to implementing a decent protocol stack.

It seems reasonable, but I sure would like to find the logic all wrapped up
in one chip. I even considered something like the XILINX chips, but too many
$$ for chips and especially for tools.

Bob Ammerman
RAm Systems
(high function, high performance, low-level software)
[and occasionally hardware, if it's digital  :-)]

----- Original Message -----
From: Dan Michaels <oricom@LYNX.SNI.NET>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Monday, June 05, 2000 11:52 AM
Subject: Re: [PIC]: External SRAM on PIC (or AVR)


> Harold wrote:
> >        There have been lots of discussions about serial SRAM on the list
over
> >the years. As far as I can tell, there aren't any of any significant size
> >out there. I WAS using the Dallas RamPort (DS1380 and DS1381) 'til they
> >discontinued them on us...  I'm now moving designs over the the PIC18c452
> >which has enough RAM for several products. On one product I'm using the
> >18c452 with several latches to drive a 128kbyte SRAM (capacitor backed).
> >That takes several chips. Seems like SOMEONE would make a reasonably
> >large serial SRAM, but that doesn't seem to be the case.
> >
>
> Bob Ammerman wrote:
> >Exactly what my search turned up - nada nil nothing none :-(
> >
>
> You can always go to a PIC with a large 68-84 pinout, like Harold
> is doing, but adequate RAM definitely *is* a problem for small PICs.
>
> Maybe nada [from practical perspective] but -->  Solutions Cubed has
> the RAMPack, which has 8Kx8, RS-232 addressable, designed originally
> for use with Basic Stamp, but expensive at $29.95 from Jameco. Can
> expand to 32K.
>
> I recently designed my own spin-off from the RAMPack. Uses 2 32Kx8
> SRAMs, controlled by a PIC64 on a small 2"x2" pcb. Addressable via
> RS-232, and also in byte-mode with address/data lines multiplexed.
> Can also be addressed in nybble-mode, so you can run off a PIC using
> as few as 8 interface lines. I just received the pcbs, but haven't
> finished the s.w. yet. I may eventually add I2C access. Estimated
> max read/write rate is 500KB/sec in burst-mode/byte-mode.
>
> This is a more difficult approach [and more expensive] than going
> to a larger pinout PIC, but I think a reasonable compromise for
> drop-in to a system with a small PIC.
>
> I had also considered going with a '4040, like Octavio, but you can't
> have multiple data buffers or random access that way. An alternative
> is 4 '161' chips, but that's a "real" PITA.
>
> best regards,
> - Dan Michaels
> Oricom Technologies
> http://www.sni.net/~oricom
> ==========================