Martin McCormick wrote:
>        I appreciate the suggestions I have heard, so far.  It
>does sound like I need a FIFO.  Actually, if I need to use
>several logic IC's, I may already have what I need.  I was just
>checking to see if there was a lazy-man's solution.
>
>        There was going to be a PIC involved, anyway, but it may
>end up taking a more active role in handling the bit stream.
>
>        I already have a 8-KB RAM chip and I believe I also have
>a suitable counter which could be used to address the 13 address
>lines on the RAM.  The idea would be to use a PIC like a 16C54 to
>handle the stepping of the counter, the reading from and writing
>to the RAM, and the serial clocking in and out of the bits.
>

Speaking of the "lazy-man's approach", this can easily be done
using a 40-pin PIC and a couple of 32K SRAM chips. There are just
enough pins on the PIC to do the addressing/etc. The PIC can
also perform all kinds of data processing/timing/etc. I just
finished such a design myself - and sent for pcbs a couple of
days ago.

3 chips total, and cheap. Any other approach, I think, would require
much more circuitry and/or expense. The main down side to the PIC
approach is gonna be top transfer rates - but 8 Ksps is no problem.

BTW, anyone know of a 64KB FIFO that doesn't cost a month's salary?

best regards,
- Dan Michaels
Oricom Technologies
http://www.sni.net/~oricom
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