Russell McMahon wrote:

>PIC EEPROM has a datasheet-specified number of write cycles before failure.
>
>While eeprom is not generally held to have a failure mode due to number of
>reads, is there any suggestion from practical experience that failure may in
>fact occur due to reads? (I KNOW there isn't but ... :-))
>
>I ask because I'm about to write a program which makes repeated reference to
>semi-permanent tabular data. I could mirror the eeprom data in RAM but it
>would be more secure not to.
>
        I thought that the EPROM cells were programmed by trapping charge
under the gate so that there is effectively a bias voltage always applied
to the gate. The failure mode would then be leakage of the charge off so
that the device would eventually (~40 yrs) return to the unprogrammed
state. Until then, I would think that you are effectively reading the state
of a logic gate that has it's input 'hardwired' to a fixed level.
        If it was me, I wouldn't shadow the ROM.

        Jim

  Elm Electronics
  ICs for Experimenters
http://www.elmelectronics.com/