On Wed, 26 Apr 2000, Peter L. Peres wrote: > Hi, > > I am trying to clock a PIC using an existing PLLs oscillator signal. The > PLL runs at a frequency between 3 and 4 MHz (depends on the application). > It has a very low signal on the oscillator pin (negative R oscillator). > After some experiments I have managed to pick off signal between the > crystal and its coupling capacitor. I propose the following schematic for > PIC clocking: > > ^VCC ^VCC > | | > | ) > / ) choke, 22uH > 4M7 \ ) > / | 220R 22pF > \ |--*--/\/\/\--||--> PIC X1 > | | > PLL Xtal <--|Xtal|---*--->|--+ > | | > PLL Xref <--| |------* === > 22pF | GND > / > \ > 1M / > \ > | > === > > I will use a JFET with low IDSS. The Upper 4M7 resistor should prevent > the JFET gate junction from rectifying. I might have to omit it if there > is not enough gain (there should be too much with this scheme imho). The > signal where the gate of the JFET would be will be about 500 mV pk-pk at > most. It could be as low as 150 mV pk-pk. > > Is there any data on the gain of the PIC oscillator gate(s) ? How little > is 'safe minimum' to drive the input ? The parts I will use are XTs. What > other (simple) amplifiers have been used to drive the PIC clock from low > signals ? AC or DC coupling ? If DC coupling then how important is > operating point vs. temperature ? Any problems with harmonics (assuming > untuned coil as above) ? Peter, Which JFET are you planning to use? What is controlling your PLL? A few years ago Mike Keitz posted a clever PLL that consisted of nothing more than a Varactor (i.e. a diode whose capacitance varies with reverse DC bias). What he did essentially was to place the varactor in parallel with one of the PIC's crystal capacitors and vary the diode's reverse bias using a very simple PWM algorithm. Now, this won't get you the ~25% variation you're seeking, but it may be worth investigating. Scott