Joe, Grif, Wagner, Dave, thank you all for the responses. I think I have been around the track a couple of times with pretty much everything you all mentioned. Bypass caps everywhere, as much physical separation between analog and digital sections as possible given a 3"x5" pcb, "separate gnd busses" for analog and digital, analog gnd single point connection returned directly to power entry point, as much gnd planing as possible on a 2 layer pcb, wide power traces, separate analog regulators, lowest feasible R values on opamp ckts, 2 opamp inverting stages in series, not using non-inverting stages, ferrite bead in power in lead and Rs-232 line. Also, pcb is in an EMI-shielded ABS case, and with case removed, the noise *is* always 2x to 3x to 5x higher. [I wonder if this isn't "the" crucial clue?]. I assume this means pickup from local digital sections of pcb is what is being shielded. I don't think it's coming from outside. ================= Some specifics: - 2 mV noise is referenced to input, with input grounded directly and measured by reading A/D output, not with scope. - for this measurement, input range = +/-1.25v, so 2 mV represents only about 9 bits - so am losing ~3 A/D LSBs. - Power train: - wall wart -> 7812 --> 7805 (digital). " --> 78L06 (analog +). " --> 7662 (-12v) --> 79L06 (analog -). - all regs bypassed, filtered high side, low side, etc. - Gnd planes present under noisy 7662 (766x derivative). Noise referred to above is broadband noise, not correlated to 7662 switching. - Analog circuitry: 2 inverting op amp stages (superior CMR to non-inverting), currently using TLE2072, 4 gains set via '4052. - Lowest range: +/-1.25v, Av1=0.4, Av2=4. - R values: 1st stage - 1M in, T-section feedback to lower effective R, with 82K-21K-68K. 2nd stage 12K in, 50K fb. - both stages switch gain via '4052 mentioned above. - output to A/D thru small R. - opamp/CMOS switch bypassed directly at pins. - A/D: LTC1400, SOIC, 12-bit, 8-pin, internal Vref, SPI control at 6.4 Mhz. Vref bypassed directly at chip. Vdd, Vss bypassed close to chip. - Digital control: PIC76 @ 20 Mhz, bypass caps in several places, gnd planes under chip, gnd island around xtal. - no hi-speed signals passing near analog circuitry. - 2 DC control signals from PIC to '4052, bypassed. - RS-232 connection to pcb: lots of noise was originally measured on the TX line from the PC, and now has a ferrite bead inline. Note - overall, this is a "system-level" problem. Mixed analog-digital, small space, noisy 7662, R values as small as I can make them, RS-232 to PC, wall wart power, etc. I have isolated and dealt with any number of noise sources already. Working on next pcb layout: - moving analog regs further away from PIC. - removing 7812 from inline with 7805. - considering moving single-point analog gnd connection from 78L06/79L06<->power_entry_point to under A/D. Note - I have several times fiddled with the opamp ckt design and R values, and they are about as low as I can go now, and still keep Rin = 1M. I may need to go to a completely different front-end design, ie FET follower amp - unfortunately this is much more complicated, requires lots more space, it drifts, etc/etc. I was hoping to keep the front-end design simple and straightforward, since BW is only 1 Mhz, but I am beginning to wonder. ============= ============= Re what Dave said: >Decouple your supplies into the op-amp. A series R and local C to ground >should work well. Bypass caps are "everywhere", but I haven't tried series R in the opamp power leads. However, they have their own regulators, bypassed and separate from the digital regs, plus a separate analog gnd, too. So I don't think a series R here will help much. ================= >Check the op-amp PSRR AT the frequency of your main interference. > >Use a spectrum analyzer to check everything, not just a scope. Measured noise is pretty wideband, not correlated to PIC xtal or 7662 - [xtal is outside passband, 7662 has been dealt with]. =============== >In the circuit itself, lower the impedances if you can, keep layout tight, >don't ground or decouple to any foreign points. I already have lowered the R values in the analog section as far as I think I can go. The 2 mV noise was measured with input BNC shorted. "... gnd or decouple to a foreign point". What does "foreign" point" mean? ==================== ==================== Re what Joe mentioned: >And yes, you may be missing something. You can trade off bandwidth for >noise! The narrower the bandwidth, the lower the noise figure. Every time >you reduce bandwidth to 50% noise is decreased to 35%. Its one of those >square law formulas I learned in Signals. I am pretty familiar with signal theory, but this is a wideband ckt, and the analog has to be made to tow the line. BW here is 1 Mhz, and I wish I could make it 20 Mhz!! [I could probably get Walter's 0.12 uV, if I LP filtered down to 3 hz. Yeah, right]. -------> My wondering was whether there isn't some magical formula saying something like "for a 1 Mhz BW, no matter how damn hard you try, you aren't ever gonna get the noise below ___ mV, unless you do ........". [as in, "make the Rs all <= 1K", whatever]. =============== >There are other exotic methods for squeezing the last little bit out of a >signal path, synchronous detectors, digital filtering, extremely long (over) >sampling, etc. My case is 1-shot waveform captures, and I want to make the ckt work as well as possible *before* the DSP stuff comes in [which it does later on]. =============== =============== RE what Wagner mentioned, I am still mulling over your comments. Lots of good info there. The Vref on my LTC1400 A/D is inside the chip, bypass caps outside. Noise measured via A/D binary output, with front-end amp tied hard to gnd. >Here again, expensive and good polypropylene caps makes a hell of a >difference from cheap ones. My only caps are ceramic bypass and electrolytic P/S filtering. Where did you use polypropylene? For coupling? ============== Whew, what a marathon. Given all this, if there is something I have clearly overlooked, ....... ???????? Best regards, - Dan Michaels