David E Arnold wrote:
.....
>Where can we read more about stray capacitance and resitor arrays, etc?
>Is there any good online introductions or reference?

Hi David,

Looking around, I found some ballpark figures for "parasitic"
capacitances (ie, stray cap to gnd) at ckt nodes:

1) From Johnson's book, pg. 307-8:
- connector, .1" pin spacing:  "a few pF between any signal pin and gnd"
- connector pads on pcb:  .5 pF
- pcb trace (50 ohm impedance):  3.6 pF/in  [note - 50 ohm Zo is low side
  for most traces, being a wide trace above a ground plane; most traces
  would have higher Zo and less capacitance, from C(pF/in)=Tpd/Zo]
- hi-speed receiver input:  2-10 pF
- 3-state driver in hi-Z mode:  "high as 80 pF"

This last is an interesting figure I wasn't previously aware of.

2) From Elantec Apnote #23, on current-mode feedback (CMF) op amps:
- to attain ~2.5 pF at input pin, gain resistors must be connected
  directly to the input pin (ie, apparently meaning zero trace length
  and very short lead lengths), and "a socket is probably too
  capacitive to use".
- for DIP package, 1.5 pF is a minimum practical value attainable for
  "external" parasitic cap at an input terminal
- "almost no CMF designs use Rf values greater than 1.3K. Higher
  frequency amps use Rf values around 300ohm to mitigate Cin problem"

Rough bandwidth estimate related to parasitics:

  F(3dB) = 1/(2*PI*1300*1.5pF) = 80 Mhz

http://www.elantec.com/pages/app_notes.html

hope this helps some,
- Dan Michaels
Oricom Technologies
http://www.sni.net/~oricom
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