Well I guess I'll weigh in with my opinion...

As far is I know the reason you want to tie off inputs to *either* Vdd or
ground is to avoid excess (and unnecessary) current drain. It happens
because the NMOS transistor and the PMOS transistor have overlapping
threshold voltages. That is, there is a voltage range where *both* the NMOS
and PMOS transistors are on producing a path from Vdd to ground. Of course
with either a Vih or Vil applied, one or the other is firmly off. I am not
aware of an oscillating condition, it seems unlikely since the inputs look
to the outside world like two capacitors in parallel and to move the pin
voltage you would have to have real charge coming in or going off, and we
said at the start that they are open. Instead, I suspect that if both of the
input diodes are similar, then the leakage current across them would tend to
put an open input somewhere around Vdd/2 which is squarely in the spot that
both input transistor are turned on.

I think you can achieve the desired effect by making all unused pins outputs
(not tri-stated) and applying either a high or a low by writing to the
concerned register. What, if any difference it makes high or low is not
clear to me.
>
> Steven Rightnar wrote:
>>
>> I have seen it everywhere (pull all unused output lines to 5 volts). OK what
>> if you dont do this? I have one curcuit that seemed to work fine and I did
>> not pull the outputs up.
>>
>> Thanks,
>>
>> Steve