Hi All,

I'm looking for an Open Source / Open Hardware solution to program
the ispLSI devices. Additionally it should be possible to prepare
the project with a HDL which does not depend on the particular EPLD family
(Verilog of VHDL).
Now i see the following possibility:

1) Prepare & test the design with Verilog, using the
    v2k (http://www.v-ms.com/)
    or ver (http://daggit.pagecreator.com/ver/ver.html)
    or Icarus Verilog (http://www.icarus.com/eda/verilog/index.html)
2) Translate the tested design into ABEL (AFAIK such functionality
   is available in the "ver" package)
3) Compile the ABEL source with the free version of ispDesignExpert
   (well, it is not Open Source :-( ).
4) Download the obtained JEDEC file into the hardware.

So I have a question regarding the point 4. Does anybody knows the Open Source
and Open Hardware solution to acomplish it? The wdownld.exe included
with ispDesignExpert requires the proprietary Download Cable (schematic
is not published).
Maybe other EPLD families (Altera, Xilinx etc.) are better suited for such
OS/OH project (ie. more friendly to OS/OH movement)?
Probably there is no EPLD family with Open Source fitter, but most vendors
provide the limited versions for free, and they may be used when the Verilog
compiler can generate the ABEL or AHDL source...

--
                        TIA
                        Wojciech Zabolotny
                        http://www.ise.pw.edu.pl/~wzab

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