>I have found numerous rs232 references on the voltages, cable lengths, connector pin-outs, etc., but nothing whatsoever on the actual signals on the wire going from one device to another. What does the actual waveform look like for instance, while transmitting the octet H'25' at 9600 baud, 8/n/1? >I have discovered through trial and error that this works when communicating to my PC at both 9600 and 4800 baud (logic levels indicated - actual levels inverted due to direct connection from 16F84 to PC): snip >My question is: Should this work? Am I just lucky, or is this a sound implementation of the standard? I know the voltage levels are questionable from a portability standpoint - it's the logic states and timing I'm questioning. > >Thanks, AND >>The frustrating part for me is that I still don't have a definitive reference for whether the start bit is 1.5t, 1t or 0.5t, and of what polarity relative to the stop bit. Does anyone have a pointer to an actual rs232 standard that shows these relationships? I know the voltages and pinouts - but what *exactly* is supposed to take place from the start of transmission to the very end? Even an ugly ASCII art diagram would be great. ++++++++++++++++++++++++ JB, Consider line idle condition to be a "1" (this is -12v for true RS232) Idle condition wiull depend on YOU for a TTL system (could be +5 or ground or ... . The important thing is to consider that "!" is the idle state. Then - - A start bit is ALWAYS a "0" - A STOP bit is always a "1" - A START bit is ALWAYS 1 bit long - A STOP bit is ALWAYS * AT LEAST * 1 bit long and may be longer. It can be 2 bits long but any length over 1 bit is OK unless you have a system in which you have defined a longer minimum time as necessary. - You must have a predefined number of data bits, each exactly 1 bit time long. - You may have a polarity bit following the data bits and before the stop bit(s) IF you have defu=ined this as part of your protocol. The 1.5 bits confusion may have come from several sources. As defined above the MIDDLE of the 1st data bit occurs 1.5 bits after the start of the START bit (all the start bit plus the first data bit). Therefore the first data sample is taken 1.5 bit times after the LEADING EDGE of the first edge of the START bit. Subsequent data samples are taken at 1 bit intervals (at 1.5, 2.5, 3.5, 4.5 ... bit times after the 1dst edge of the START bit.) Draw a picture - it makes sense. X = line idle condition S = START 0-7 = data s = STOP S is opposite of X s is same polarity as X Each bit here is shown by TWO characters. XXXXSS0011223344556677ssXXXXXX Sampling should ideally occur in the middle of the bit. Data bit 0's middle occurs after SS0 = 1.5 bits Data bit 1'2 middle occurs after SS001 = 2.5 bits etc. Bit 0 is always sent (and received) first. Some formats only use 7 data bits (with or without parity). Systems with parity usually don't use 8 data bits. SOME systems effectively use 9 bits with the 9th bit used to indicate an address word. An additional thing to be aware of - You can drift by no more than 1/2 a bit across the whole word when sampling. If you DO drift by more than 1/2 a bit you will drift into the edge of the next bit which will give you an error. (Actually MAY give you an error but if it doesn't it's only by luck). Russell McMahon _____________________________ >From other worlds - www.easttimor.com www.sudan.com What can one man* do? Help the hungry at no cost to yourself! at http://www.thehungersite.com/ (* - or woman, child or internet enabled intelligent entity :-)) -----Original Message----- From: JB To: PICLIST@MITVMA.MIT.EDU Date: Monday, 27 March 2000 11:18 Subject: rs232 works - should it? >I have found numerous rs232 references on the voltages, cable lengths, connector pin-outs, etc., but nothing whatsoever on the actual signals on the wire going from one device to another. What does the actual waveform look like for instance, while transmitting the octet H'25' at 9600 baud, 8/n/1? > >I have discovered through trial and error that this works when communicating to my PC at both 9600 and 4800 baud (logic levels indicated - actual levels inverted due to direct connection from 16F84 to PC): > >high 1t >low 0.5t >bit 0 1t >bit 1 1t >bit 2 1t >bit 3 1t >bit 4 1t >bit 5 1t >bit 6 1t >bit 7 1t >high 1t > >My question is: Should this work? Am I just lucky, or is this a sound implementation of the standard? I know the voltage levels are questionable from a portability standpoint - it's the logic states and timing I'm questioning. > >Thanks, > >JB >