On Fri, 24 Mar 2000 08:47:47 -0600 (CST), you wrote: > > >On Fri, 24 Mar 2000, Cor Grooff wrote: > >> On Fri, 24 Mar 2000 13:47:40 +1200, you wrote: >> >> >From: Edson Brusque >> >> I'm making some research for a future product and want to know if >> >>there's a chip that can generate 8 PWM outputs at high frequency (say, >> >>30KHz) based on a serial input. It have to work as some kind of 8-channel >> >>DAC, but outputting PWM and not linear voltage. >> > >> >> How about a CPLD ? >> >> Macrocell counts for 8 PWM's are: >> 6 bit resolution : 62 >> 7 bit resolution : 71 >> 8 bit resolution : 80 >> 9 bit resolution : 89 >> 10 bit resolution : 98 >> >> >> 64-cell CPLD's can be had for as little as $2 (altera) >> >> C > >But is it possible to run the pwm counters at full speed with so few >macrocells? My experience with altera is that a 6-bit counter is about the >widest possible (for a clock of around 40Mhz). Cascading counters is relatively >expensive (but not prohibitively so - 16bit counters at the full clock rate are >possible. They just eat up more resources.) > >Scott The above cell counts assume a shared counter and 2^n period If you require variable/independent period for each PWM then it would take about 3 cells/bit/pwm (counter/period/duty). @ 8bit: 3* 8*8 -> 192 + glue -> 256 cell CPLD @10bit: 3*10*8 -> 240 + glue -> 256 cell CPLD (too!) Problem here is that you're stuck with a 10000 pin TQFP, of which about 9999 pins would be "NC" ;-) Synchronous counters are easy, take one product term at each stage. 8 bit ctr: 30 kHz * 256 steps = 7.78 MHz clock 10 bit: 30.72 Mhz, all well within device specs. If this will be more than a one-off have a look at www.clear-logic.com C