To implement ICD they need A) breakpoint registers to cause an interrupt when PC = registers. Two will do. B) copy of the PC after an external interrupt occurs. The ICD connects to the '877 only by RB6&7 so that's what must trigger a copy of the PC into these two registers. C) Single step, which is just breakpoint at the next instruction? except for conditional skips, but if your just before the skip you can predict the action of the conditional right? So....If there are two registers reserved... that what they are... James Newton mailto:jamesnewton@geocities.com 1-619-652-0593 phone ----- Original Message ----- From: Tony Nixon To: Sent: Thursday, February 24, 2000 20:13 Subject: Re: F87x register aliasing > Scott Dattalo wrote: > > > > According to the data sheets I just downloaded a few days ago, the > > F873/F874 alias addresses 0x120-0x17f back to 0x20-0x7f and similarly > > 0x1a0-0x1ff to 0xa0-0xff. In other words, general purpose ram accesses in > > bank 2 will actually access bank 0 and accesses in bank 3 will access bank > > 1. > > > > Fine. > > > > However, the F876/F877 appear to take a different approach. First of all, > > they have real ram in the upper banks, but they still shadow a block of > > addresses. Specifically, the upper 16 bytes in banks 1,2, and 3 are > > aliased to bank 0. Is this right? Wouldn't it make more sense (or at least > > be more consistent) if the upper 16 bytes of bank 1 were not aliased to > > bank 0 and the upper 16 bytes of bank 3were aliased to bank 1? > > > > Scott > > Sounds right by the data sheet, but isn't it funny that the 16F874/873 > has references to the common upper 16 bytes but not drawn in the map??? > > I wonder what RAM locs 18E and 18F are reserved for??? > > I wonder if the F8XX series have hidden instructions to access the stack > like the 18CXXX do. Be easy for ICD then. > > I wonder if it's time to go home :-) > > -- > Best regards > > Tony > > http://www.picnpoke.com > mailto:sales@picnpoke.com