John Orhan wrote:

> I am trying to wrap my head around the paging system that the '505
> uses. If I understand correctly, the memory is banked into four arrays
> of around 255 bytes each.

  First you must decide whether you are speaking of RAM (working
variable storage) or program memory = EPROM.  I am pretty sure you mean
the latter.

  The program counter is in two parts (not quite halves).  The low part
is 8 bits, so if the chip has 1024 words of program memory, then the
high part is 2 bits.  Except for branch instructions, program execution
proceeds through the whole program memory one location after another and
loops from the last program location back to zero and continues.

  The return stack saves all bits of the program counter, so you always
return from a RETLW or a RETI to the point of calling.  If however you
want to GOTO or CALL a routine, the GOTO or CALL instruction, depending
on the particular chip (sub-family) may or may not contain all the
address bits.

  On 12-bit instruction chips, bit 7 is missing from CALL instructions
but not GOTOs, so you simply cannot call a subroutine in the second half
of a "page" (256 bytes - exactly).

  Otherwise, whatever bits are not contained in the GOTO or CALL
instruction are picked for the high Program Counter byte from the
register called PCLATH (or two of the status bits on the 12-bit cores).
If you want to GOTO or CALL a routine on a chip where there are less
bits stored in the GOTO or CALL instruction than the PC, you must set
set PCLATH to correspond to the high address bits of that page.

  Note that on many chips, the GOTO or CALL instruction contains all the
necessary bits.

  Note also that if you change the low Program Counter by using it as
the destination of an operation, the high PC will be loaded from PCLATH
in the process, so you must also set PCLATH correctly prior to doing
this.  It initialises to zero, so you may *not* need to set it if you
want to branch to page zero and have never set it otherwise.
--
  Cheers,
        Paul B.