Dan, What's the Microchip supplied module? you mean code? is source available? can you decompile it if not? Debug overhead really doesn't matter as most time is spent waiting for the wetware to cycle. Nice unit (1-chip testbench) you have there! Lots of function for little price. Now, if you can just add device programming, bootloader (have to go open source for that don't you?), monitor, debug, and improve your user interface software.... What do you sell the bare board for? Tony, That is really interesting code. Correct me if I'm wrong but the ISR can't see what the PC was before the interrupt can it? Can you read the stack? Scenix has a shadow register that stores the w, PC and something on a int IIRC. Reduces interrupt latency? Does the '877 have such a thing? Undocumented? --- James Newton mailto:jamesnewton@geocities.com 1-619-652-0593 http://techref.massmind.org NEW! FINALLY A REAL NAME! Members can add private/public comments/pages ($0 TANSTAAFL web hosting) -----Original Message----- From: pic microcontroller discussion list [mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Dan Michaels Sent: Thursday, February 17, 2000 07:57 To: PICLIST@MITVMA.MIT.EDU Subject: Re: An Idea.... Importance: Low Tony Nixon wrote: >> >>James Newton wrote: >> >> I was wondering if the ISR could be setup to allow only one >>instruction of the main code to execute when the ISR returns. [snip] > >IRQ bcf intcon,t0if > ; process anything here > clrf tmr0 > decf tmr0 > nop > retfie > >start bsf status,rp0 > movlw b'11000000' > movwf opton ... Tony, Your code idea looks interesting, but don't you need something like b'11000001' (prescale TMR0 by 4) in the option register to make the INT occur at the right time on return? Unfortunately this method commandeers the most critical resource in the PIC - namely TMR0, but might be worth playing with. It does clearly show how much overhead is required to implement debug - 1 for execution, 10-to-20-to-50 for overhead. =============== James, Your questions are answered. No need for fancy work-arounds. I looked at the specs for the '87x chips, and Microchip saw the light and finally implemented what I described yesterday was present in the 8088s since birth - built-in debug mode. The info is sketchy, but you set a bit in the config reg during program- ming (like the trap flag on the 8088), load a Microchip-supplied module in the last 100h bytes of code space (like the INT 1 ISR on the 8088), and use RB6,7 for control (got to talk to it somehow). When I built my own PIC Monitor chips, I specifically did not add any Go/Step/Disassemble/etc commands like 8051 & other monitors use, simply because the others can use external program ROM/RAM while the PIC cannot. So instead, I built into the command set many of the other features you've been describing the past couple of days - o'scope, logic analyzer, reg/port read/write, PWM, generator, and pulse counter modes - and billed it as a "1-Chip TestBench", useful for testing target hardware (external to the cpu) before/while the firmware is being written. - Dan Michaels Oricom Technologies http://www.sni.net/~oricom