Thanks Tom, I've added a link to this post. I think that this would be a
nice addition (like Randy Glenn's mention of external ram and PLLs) to a
more upscale version of the CUMP/EBB idea. I'd like to concentrate on the
base version for now, but I certainly see that one day our new PIC user will
have a project that needs a faster logic analyzer than the 1 or 2 MHz that
he can get with just the '877 and our programs, so he will look for an find
a way to add some external ram and your Trigger comparator.

---
James Newton mailto:jamesnewton@geocities.com 1-619-652-0593
http://techref.massmind.org NEW! FINALLY A REAL NAME!
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-----Original Message-----
From: pic microcontroller discussion list
[mailto:PICLIST@MITVMA.MIT.EDU]On Behalf Of Tom Handley
Sent: Tuesday, February 15, 2000 03:50
To: PICLIST@MITVMA.MIT.EDU
Subject: Re: An Idea....
Importance: Low


At 03:31 PM 2/14/00 -0800, James Newton wrote:
>Exactly! YES YES YES. See
>http://techref.massmind.org\idea\ebb.htm
>especially the last bullet point under "In the CUMP project"
>
>The upshot is that I think a $10 board consisting of a '877, MAX 232,
Analog
>front end, PWM output filters and power regulators could provide the
>following:

[snip]

   Jim, if you are going to do such a board, I designed a simple 24-Bit
Trigger Comparator as part of a Logic Analyzer block that may be of use. The
following is a `snippet' from the docs:

   - Tom
---------------------------------------------------------------------------

   This is a 24-Bit Programmable Comparator with Bit-Enable qualifiers. It
uses an SPI-style serial interface to load the Bit-Enable qualifiers and the
Comparator data. This data is compared with the 24 Inputs to generate an
Equality Output. Inputs with their corresponding Bit-Enables cleared are
ignored. It also provides a Serial Data Output and an Enable Input to
support expansion. One application is a 24-Bit Trigger Comparator in a Logic
Analyzer.

   The design is implemented in a Lattice Semiconductor ispLSI1016E-100LJ
CPLD using a 44-pin PLCC package. The device features +5V
In-System-Programming. To program the device you need to download the free
ISP Daisy Chain Download software from Lattice Semiconductor at:

      http://www.latticesemi.com

   If you don't have the Lattice buffered ISP Download Cable, plans for
building one are at:

      http://www.teleport.com/~thandley/Wilbure.htm

Hardware Interface
==================

   Inputs:

      TC0 - TC23 = Comparator Inputs.
            SCLK = Serial Clock Input. Clocks on Rising Edge.
             SDI = Serial Data Input.
              EN = Enable Input for Expansion. High = Enabled.

   Outputs:

              EQ = Comparator Output. High = True.
             SDO = Serial Data Output for Expansion.

   From a software standpoint, you send 48 Bits (MSB-first). The first
24 Bits are the Bit-Enable Qualifiers. High = Enable. The next 24 Bits are
the Comparator Data.


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)