On Mon, 7 Feb 2000, Rich Leggitt wrote:

> On Mon, 7 Feb 2000, Scott Dattalo wrote:
>
> > actually, it's 13 cycles if you take the call and return into account and
> > 11 cycles w/o call.
> Really? What am I missing?

I was counting time along the wrong path of execution. You're right. I
also optimized for the wrong path (and there were two polarity errors with
the Z bit). Okay I got the mistakes out of the way.


dec32:
    movwf   FSR0L    ; the fsr's (three of them) on the 18cxxx
    clrf    FSR0H    ; are 16bits wide

    decf    POSTINC0,F,1 ;Indirect access that increments the fsr.

    bnz      dec32nz     ;this was bz

  ;The lsbyte is zero , so we don't need to propogate the borrow
  ;but we need to see if the higher bytes are zero.

    movf    POSTINC0,w,1 ;The first byte is zero
    iorwf   POSTINC0,w,1 ;check the next three
    iorwf   POSTINC0,w,1

    return

dec32nz
   ;decf on the 18cxxx parts affects C

    skpnc
     return

    decf   POSINC0,F,1
    skpc
     decf  POSTINC0,F,1

    skpc
     decf  POSTINC0,F,1

    clrz          ;was setz
    return

-------------

On Mon, 7 Feb 2000, Rich Leggitt wrote:

> On Sun, 6 Feb 2000, Dmitry Kiryashov wrote:
>
> > Here is 32bit increment counter. It's a little bit shorter so it can
> > be used if time|memory is critical.
>
> Hey, I like it, all I have to do is negate the initial counter value
upon
> receipt:
>
> neg32:  movwf FSR               ; 32 bit 2's complement
>         comf INDF,f             ; i.e. invert and increment
>         incf FSR,f
>         comf INDF,f
>         incf FSR,f
>         comf INDF,f
>         incf FSR,f
>         comf INDF,f
>         ; fall thru
> inc32:
>         movwf   FSR
>         clrz
>         incfsz  INDF,F
>         return
>         incfsz  FSR,F
>         incfsz  INDF,F
>         return
>         incfsz  FSR,F
>         incfsz  INDF,F
>         return
>         incfsz  FSR,F
>         incf    INDF,F
>         return

 this would look like:
neg32:
    movwf  fsr0l
    clrf   fsr0h
    comf   postinc0,f,1
    comf   postinc0,f,1
    comf   postinc0,f,1
    comf   postinc0,f,1

inc32:
    movwf  fsr0l
    clrf   fsr0h
    clrz
    incfsz postinc0,f,1
     return
    incfsz postinc0,f,1
     return
    incfsz postinc0,f,1
     return
    incf   postinc0,f,1
    return


another way:
inc32:
    movwf  fsr0l
    clrf   fsr0h
    subwf  wreg,w,1     ;zero W and set the carry
    addwfc postinc0,f,1
    addwfc postinc0,f,1
    addwfc postinc0,f,1
    addwfc indf0,f,1

    movf   postdec0,w,1
    iorwf  postdec0,w,1
    iorwf  postdec0,w,1
    iorwf  indf0,w,1

    return

but it's a cycle longer. (but it's isochronous, and could be cascaded
since fsr0 points to the beginning byte).

Scott