On Sun, 6 Feb 2000, Dmitry Kiryashov wrote:

> Hi Rich.
>
> incf FSR,F will destroy zero flag.
> Let's try to use incfsz FSR,F instead.
>
> WBR Dmitry.
>
>
> PS. modified variant of your code:
>
> ; given address of 32 bit little-endian counter in W,
> ; decrement the counter and return Z set if zero
> ; 99.2% of the time, this takes 10 cycles w/call

actually, it's 13 cycles if you take the call and return into account and
11 cycles w/o call.

> dec32:
>         movwf   FSR
>         decfsz  INDF,F
>         goto    dec32nz
>
>         incf    FSR,F
>         movfw   INDF
>
>         incf    FSR,F
>         iorwf   INDF,W
>
>         incf    FSR,F
>         iorwf   INDF,W  ;get _Z finally
>         return
>
> dec32nz:
>         clrz            ;set _Z=0
>         incfsz  INDF,W
>         return
>
>         incfsz  FSR,F   ;doesn't corrupt _Z
>         decfsz  INDF,F
>         incfsz  INDF,W
>         return
>
>         incfsz  FSR,F   ;...
>         decfsz  INDF,F
>         incfsz  INDF,W
>         return
>
>         incfsz  FSR,F   ;...
>         decfsz  INDF,F
>         return
>         return
>


If Dmitry's optimized then chances are nobody can do much better. However,
I thought it'd be interesting to see this same thing done with 18cxxx
instruction set. I know it doesn't help you in the least, but it is
instructional

; 10-16 cycles

dec32:
    movwf   FSR0L    ; the fsr's (three of them) on the 18cxxx
    clrf    FSR0H    ; are 16bits wide

    decf    POSTINC0,F,1 ;Indirect access that increments the fsr.

    bz      dec32nz

    movf    POSTINC0,w,1
    iorwf   POSTINC0,w,1
    iorwf   POSTINC0,w,1

    return

dec32nz
   ;decf on the 18cxxx parts affects C

    skpc
     decf  POSTINC0,F,1

    skpc
     decf  POSTINC0,F,1

    skpc
     decf  POSTINC0,F,1

    setz
    return


There are probably a couple of things you can do to minimize the second
part...

Scott