Martin McCormick wrote:

>   Since the TMR0 register has to be stuffed with a count to keep the
> samples coming at the right rate and jitter could also be introduced
> there, that pretty well dictates that the very first two things I do
> in the ISR is to stuff TMR0, ...

  Presumably using no prescaler, and performing an ADDWF on the timer
rather than simply loading a value.  The combination of these two
nicely compensates for interrupt latency.
--
  Cheers,
        Paul B.