Andrew Warren wrote:
> Jeffrey Siegel <jeffrey.siegel@activecenter.com> wrote:
>
> > I'm trying to create an interrupt every millisecond...and I'm
> > really really close, but not perfect....
> > ....
> > I did check the listing file and the compiler is putting 0xEC78
> > (decimal -5000) into the TMR1L/TMR1H counter.
>
> Jeffrey:
>
> The inaccuracy is caused by the delay between the Timer1 timeout and
> the reloading of the TMR1H:L registers in your interrupt-service

And by the possible clearing of the Timer1 prescalers on a TMR1 write.
Both timer0 and timer2 clear their prescalers on their counter register writes, so
it may be another undocumented 'gotcha' for timer2 since no mention is
made about the timer2 precaler one way or the other in any of the doc I've read.

Given the other bugs in MPSIM I wouldn't trust what I'd see unless I actually
MEASURED it on real hardware.

> routine.  In other words, by the time you get around to resetting it
> to -5000, Timer1 has already counted past 0 (it's counted all the way
> to 46, judging from the comments you made later in your message).
>
> You can fix this two ways:
>
>     1.  Instead of loading TMR1H:L with -5000, load it with THE
>     CURRENT VALUE OF TMR!H:TMRL MINUS 5000.  That'll compensate for

Which is best handled with an
ADDLW TMR1L
instruction. That way you're automagically including the exact offset
at the time of the reload (since you started out with 0 at the instant of
overflow/interrupt). Be careful about carry from TMRL to H. It might be wise to
read TMR1L and if it's about to roll over (~F8) execute some nop's so that you
know that your add carry into TMR1H will be correctly done. Basically you need
to be certain that your add carry instructions will not have a counter carry
within them. If you KNOW that you aren't anywhere near overflow then just do
the single Add.

>     the additional Timer1 counts that will have occurred before the
>     ISR loads the registers.
>     2.  Use the Timer1 "Compare" feature, as documented in the "CCP
>     (Compare/Capture/PWM)" section of the data sheet.

This is the better way to get really precise timing. You have a choice of
automatically clearing timer1 on compare match and generating a software interrupt
(special trigger mode), or if you're doing A/D using CCP2 to trigger the A/D precisely
to get ZERO jitter.

Hope this helps.

Robert.Rolf@UALberta.ca