On Mon, Jan 17, 2000 at 03:45:24PM -0600, Matt Burch wrote:
> I understand that part of the ICSP spec says not to let more than 72 clocks
> go by while MCLR is being pulled from ground to Vpp, but since that is
> under control of the software it is out of my control... what can I do to
> make this work?

Use a different software programmer.  Got Linux?  Try picprg.  At least
you can review the code and _prove_ it is raising Vpp at the right time
with respect to Vdd.

Otherwise, see if you can write a PIC program to measure the time
between two pins going high, and then connect it another way to the
programmer to measure how long Vpp is taking to rise.

Hrm, thinking about this ... the programmer can either hold MCLR to
ground, with the PIC reset, or it can raise it to Vpp.  I do not think
it can make it move slowly.  So it can't be responsible for the problem.

Check your Vpp is adequate; a fault there can cause this symptom.
Your PIC will draw more current from your Vdd supply if it manages to
oscillate.  Check your supply voltage stability and decouple it well.

--
James Cameron   mailto:quozl@us.netrek.org   http://quozl.us.netrek.org/