>I tried to divide 23 bits to 15 bits with FDX2315U
>subroutine from Application Note AN617. Unfortunately
>I received wrong results.

Could you give an example?


>Does anyone have working subroutine for such divide
>(23/15 or 24/16 bits).


I would expect the routines in AN617 to work but haven't personally tried
them.

I do have a divide routine that I know works but it is for 64-bit float
(with 56-bit mantissa).  It would be relatively easy to chop out the integer
divide routine (the DLOOP64 loop and the 2 instructions above it which set
the loop counter) and reduce the precision.  It is here if you are
interested (subroutine FPD64H):

http://kdsl32.dnvr.uswest.net/cgi-bin/tl.exe/AERC/poscalc/math1h.asm

Note that it does use some instructions specific to the 16-bit core devices
(17Cxxx) and also requires the following definitions to be included
upstream:

#define _C ALUSTA,C
#define _Z ALUSTA,Z
#define EXPBIAS 0x7f

I think I have a 14-bit core version lying around somewhere that I could dig
out if anyone is interested.


Regards,

Ken