Nikolai Golovchenko wrote:

> Scott, do you have a better way to build PLL?

Maybe. But not for the general case.

But I think there are a couple of problems being discussed. First there's
filtering and then there's phase locking. If you know what the frequency the
incoming signal is supposed to be, then you (probably) don't need a 'pll'. A
simple edge synchronization algorithm is sufficient. You may want to still
filter the incoming data with the majority filter. However, the filter needs to
run at every sample. For example:

 -- sample a bit
 -- if the sum of the last k bits is greater
    than THRESHOLD then the next bit is 1, other-
    wise it's 0.

a really simple (but inefficient) sum of the last 4 bits would be:

  ; Put the sample into the carry

    clrc
    btfsc  PORT,BIT
     setc

  ;the last 8 samples are stored here:

    rlf    sample_buffer,f

  ;add the last 4 samples together

    clrf   bitsum

    btfss  sample_buffer,0
     incf  bitsum,f

    btfss  sample_buffer,1
     incf  bitsum,f

    btfss  sample_buffer,2
     incf  bitsum,f

    btfss  sample_buffer,3
     incf  bitsum,f

    movlw  -THRESHOLD
    addwf  bitsum,w
    rlf    latest_sample,f

This can be made smaller
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