There could be exists a other problem, too with the RETFIE command, because
of the setting of GIE bit, perhaps this is also a
read-modify-write operation.

From: "Morgan Olsson" <morgans.rt@TELIA.COM> Sent: Sunday, December 19, 1999
12:49 PM
Subject: Re: Theoretical problem with interrupts?


>Hej Jan Erik Bertram. Tack fvr ditt meddelande 20:00 991218  enligt nedan:
                Aha!
>>Perhaps there is a simple mistake in my consideration.
>>Is it possible, that the PIC lose sometimes interrupts by clearing
>>interruptflags?
>>If an interrupt occurs (example: Timer0Int) you have to clear the falg-bit
>>in the INTCON register.
>>but if you clear it and then at cycle Q2 or Q3 a new interrupt (example
>>RB0/INT) occurs it will be delete.

>In other words, simply: what happens if an interrupt that shall set an
interrupt flag in a interrupt flag register, occours during state >Q2-Q3 of
the BCF we use to clear another interruptflag in that same register.
[...]
>Also, i have ideas where i could benefit from BSF-ing interrupt flags to
effectively softwaregenerate interrupts.
>The same problem here: an interrupt trig during Q2-Q3 of the BSF flag will
be lost, as the flag it want to set will be overwritten >by the previous
value, that the BSF instruction read-restore...