Hej Jan Erik Bertram. Tack fšr ditt meddelande 20:00 991218  enligt nedan:
>Perhaps there is a simple mistake in my consideration.
>Is it possible, that the PIC lose sometimes interrupts by clearing
>interruptflags?
>If an interrupt occurs (example: Timer0Int) you have to clear the falg-bit
>in the INTCON register.
>but if you clear it and then at cycle Q2 or Q3 a new interrupt (example
>RB0/INT) occurs it will be delete.

In other words, simply: what happens if an interrupt that shall set an interrupt flag in a interrupt flag register, occours during state Q2-Q3 of the BCF we use to clear another interruptflag in that same register.

It is clear that it will be overwritten by the previous value, that the BCF instruction read in beginning of execution, and restores in end of execution!

I have the same worries.

However, if there is some logic that delays those interrupt signals, and set the flags only always effectively in "between" instruction executions, then we would be safe.  However I can«t see that simple expression stated anywhere in PIC documentation!!

Looking at the block schematics of TIMER0, i see a "two cycle delay 
/ sync to internal clocks" before the counter and i think that will take care of it, so the setting of the TIMER0 flag always occours during other Q than 2 or 3.  (i hoipe thet is the idea of it, as it also enables us to read the TIMER0 counter)

However I can«t see it clearly, and i would like somebody elaborate on this, and preferably i want a statement from Microchip...

According to the block schematics the PortB int on change is level, so if we only guarantee the duration ocf mismatch to be >2Q + flag setting minimum pulse time (total probably 1 full machine cycle is enough), then we will be safe.

However I am a worried about interrupt pin as i have not seen any synchronization functions in documantation.

But in the text i found: "For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles."

And that could imply there is a synchronization afterall, just Microchip forget (or for some reason don«t want?) to show that very crucial thing in the block schematics!

I really wonder about other external interrupts such as UART Rx, SPI module in slave mode, etc.  Are theese also synchronized?!

And are all internally clocked devices realy safe?

If we for once could get a clear documentation on this, we could feel safe and not waste code and execution time on cover for potential misses.
Not to mention all test we really ought to make to make *very sure* it *never* fails...

Also, i have ideas where i could benefit from BSF-ing interrupt flags to effectively softwaregenerate interrupts.

The same problem here: an interrupt trig during Q2-Q3 of the BSF flag will be lost, as the flag it want to set will be overwritten by the previous value, that the BSF instruction read-restore...


Regards
/Morgan