Perhaps there is a simple mistake in my consideration.
Is it possible, that the PIC lose sometimes interrupts by clearing
interruptflags?
If an interrupt occurs (example: Timer0Int) you have to clear the falg-bit
in the INTCON register.
but if you clear it and then at cycle Q2 or Q3 a new interrupt (example
RB0/INT) occurs it will be delete.

Example:

init:
    INTF=0;
    INTE=1;        // RB0/INT interrupt enable
    T0IF=0;
    T0IE=1;        // Timer0 interrupt enable

ISR_Routine:
    T0IF=0;        // if exactly now an RB0 interrupt occurs, the PIC will
delete it too because of the read-modify-write behavior.
                        // The PIC loses the RB0 Int

Ciao
    Jan Erik Bertram