Untested, for discussion!

This delay routine has a 1 cycle resolution variable controlled delay
Input value in counter, range 4-255 (0=256, 1=257, 2=258, 3=259) cycles
Technique: let the 2 lsb control a "table jump" to add 0-3 cycles, and use a 4cyc loop for the more significant bits.
Also, add the overhead of call, return and 10 (if i calculated correctly?) cycles for the calculations before the table and loop.

DELAY   movf counter,W  ;Get original counter in W for later use of bit 0 and 1

        BCF STATUS,C    ;Divide by four
        RRF counter     ;
        BCF STATUS,C    ;
        RRF counter     ;

        ANDLW %00000011 ;Add relative delay according to two LSB in original counter
        XORLW %00000011 ; 3 - W -> W
        ADDWF PC,F      ;Cycles relatively added:
        NOP             ;+3 cyc
        NOP             ;+2 cyc
DELAYL  NOP             ;+1 cyc & 4 cycle delay loop begin
        DECFSZ counter  ;+0 cyc
          GOTO DELAYL
        RETURN

This is a verison with 10 bit resoulution: 
counterH contains the 8 MSB, counterL the 2 LSB
Also note the code size and overhead are *reduced*!
Even more optimization possible: if the routine that calculates counterL, also do the subtraction for the table, so the XORLW can be excluded from below.


DELAY   movf counterL,W ; the number of cycles to add (0..3) (or enter with counterL in W)
        XORLW %00000011 ; 3 - W -> W    (or this calculaiton id done before)
        ADDWF PC,F      ;Cycles relatively added:
        NOP             ;+3 cyc
        NOP             ;+2 cyc
DELAYL  NOP             ;+1 cyc & 4*counter cycle delay loop begin
        DECFSZ COUNTER  ;+0 cyc
          GOTO counterH
        RETURN


To get 11 bit resolutiuon we can add 4 entries in the table, controlled by 3 bits in counterL, so the table delays 0..7 cycles, and change the loop to 8 cycles:



DELAY   movf counterL,W ; the number of cycles to add (0..7)
        XORLW %00000111 ; 7 - W -> W
        ADDWF PC,F      ;Cycles relatively added:
        NOP             ;+7 cyc
        NOP             ;+6 cyc
DELAYL  NOP             ;+5 cyc & 8 cycle delay loop begin
        NOP             ;+4 cyc
        NOP             ;+3 cyc
        NOP             ;+2 cyc
        NOP             ;+1 cyc
        DECFSZ COUNTER  ;+0 cyc
          GOTO counterH
        RETURN


Add 8 more entries to get 12 bit; 4 bits in counterL

Longer tables possible but code space eating...
so, then, if wee need it, we shold consider other solutions.

One thing to remember: counterH may not be zero, then the loop instead loops 256 cycles.
If needed to cope with CounterH=0, add instructions to check counterH.  Maybe "if CounterH=0, then goto antoer routine just consisting of a jump tree as above without the loop at the end. Maybe needed to Patch in NOPs in either branch to align their different overhead.

Somebody might want to show a solution?

Comments / optimization ideas? 

Regards
/Morgan

Morgans Reglerteknik, HŠllekŒs, 277 35 KIVIK, SWEDEN
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