In article <38167DCE.5D2B89C4@earthlink.net>, Wagner Lipnharski writes Gosh! Somebody bookmarked my post. Fame at last. Hope I got it right! Wagner, I agree with everything you say, especially about non-documented features, but I think you missed my logical flow. Initially I HAD to adopt a non-standard procedure because the ITROM VF displays just would not work using the 2-cycle poll. My analysis was that these displays (non-44780 controller) did not internally execute the 2-phase cycles when BUSY was high. Every time you pulsed E you got the same result (bits 4-7). The BUSY flag could drop on ANY polling cycle. Then you had to do one more cycle (returning bits 0-3) to get back to the rest state. In other words, there could be an odd number of polling cycles involved. So if you use the "official" method, and if the internal BUSY flag happened to drop after what you thought was the 2nd cycle, then the next E cycle, which YOU would be expecting to return bits 4-7, would actually be returning bits 0-3, and returning the LCD to the rest state. Now you are out of sync and up the creek. It was this which then led me to try static polling of the D7 bit, and then to see if it would also work on the HD44780 controller. You are probably correct in saying I should maintain 2 versions of the code, but so far it seems to work fine on both these chips. I need to so some maintenance on this product shortly, if anybody is interested I can do some more tests. Here's the (trimmed) snippet, note the static polling of bit 7. ;******************************************************************* ; Wait, testing busy flag, until LCD free. Need to complete the ; double nybble cycle even though we only need bit 7. lcd_wbusy bcf LCD_RS bsf LCD_RW bsf LCD_E ; Clock out MSD nop ; Make sure it's stable lwbtst btfsc LCD_BUSY ; Just wait for BUSY goto lwbtst ; to drop bcf LCD_E bsf LCD_E ; Clock out LSD bcf LCD_E return -- Alan Hall, Ipswich, UK