Alan Hall wrote:
[snip]
> To make a long story slightly less long, it seems (empirically) that
> when the VF module is polled for busy, in 4 bit mode, the normal
> requirement to always complete the twin cycle by polling for the second
> nibble does not apply - every poll returns the upper nibble only. That's
> UNTIL the busy flag drops, when you need to then read the other nibble
> before returning. So the standard code had a 50% chance of exiting in
> the wrong nibble phase.

Now *THAT* is something new, I need to check it out sometime. What Alan
said (long ago), was that LCD modules never supply the lower 4 bits of
the AC (Address Counter) while BUSYFLAG is up (controller unavailable).

Hitachi documentation says that the Enable (E) line is not internally
executed while BUSYFLAG is up, *EXCEPT* during reading the BUSYFLAG &
ACC Address. They are not specific if during reading the BUSYFLAG (and
if it is up) the ACC is invalid or should be discarded, because you can
not read the second nibble, thus the last 4 bits, or  otherwise.

Hitachi says literally:
"When interface data is 4 bits long, data is transferred using only 4
buses of DB4~DB7, and DB0~DB3 are not used. Data transfer between the
HD44780 and the MPU completes when 4-bit data is transferred *twice*.
Data of the higher order 4 bits (contents of DB4~DB7, when interface
data is 8 bits long) is transferred first and then lower order 4 bits
(contents DB0~DB3 when interface data is 8 bits long)."  There is no
text saying; "except when reading the busyflag that only high order 4
bits are transferred while BUSYFLAG is up..."

Until I test it I can not assume nothing, except that if something is
not documented, anything is possible, including differences from one
manufacturer to another.  There are different LCD controllers around,
not only the Hitachi HD44780, there is the Sansung KS065, the OKI M5259
and others,  Each one obeys the same commands of the HD44780, but *only*
what is documented of course.  Things not described at the "book" can be
done differently in each one, so one of them can "gate" only the
BUSYFLAG when it is up and forget the rest, since the user will keep
polling until it is down, no one would consider relevant the second
reading for the lower AC bits, so, they trick the customer, but since
the customer will be reading it twice, will never notice the problem,
and they save few gates inside the controller.

So, until tests clear this up, I would continue issuing two [E] pulses
in 4 bits mode to read the BUSYFLAG, the first to get the BUSYFLAG and
the second do skip the lower AC bits, just for precaution.

--------------------------------------------------------
Wagner Lipnharski - UST Research Inc. - Orlando, Florida
Forum and microcontroller web site:  http://www.ustr.net
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