I read the TMR0 interrupt discussion about latency and jitter.
Indeed the interrupt is delayed by one instruction cycle when it occures
during a branch instruction.
But there is a simple yet elegant solution to make it jitter free.
Insert the following two instructions at the top of the interrupt routine:

;
;
;
        ORG    04H
ISR
        BTFSC  TMR0,0   ; Interrupt occurred during branch?
        GOTO   $+1      ; Waist one extra cycle


After this sequence the interrupt timing is jitter-free!

This works only for a free running (no prescaler) TMR0.
I have this knowledge from the excellent Application note AN654 (Software
PWM).

Brgs,
Mark Langezaal