Thanks for clarifying that. Could have had a lot of problems. I'm thinking I'll use the mov w, -100; retiw sequence recommended by parallax with no prescaler. This seems pretty easy and modifiable. The only problem is if the interupt handler takes more than 97 (or so) inst. I could miss a cycle. If this is a problem, I can simply test for a new cycle at the end of the interrupt, but I can't see this being a problem. I will do start bit detection via the Falling edge detection circuitry, however, I will simply poll the edge detect bits rather than using interrupts as edge detects are not time critical (they just log a cycle for checking on) and this will eliminate interrupt source checking. Certainly the extra RAM of the 48\52 would be lovely, I would like to have more than the 136bytes RAM (I wish Scenix would release a couple of 18\28 DIP chips with more than 136bytes RAM) but the SMD only thing is a bit of a problem. Hopefully I can get by on 8 (4IN, 4OUT) 8byte FIFO's. With 50MIPS I shouldn't have stuff sitting in FIFO's for too long as long as the other end can keep up. I've started writing the input, and it seems pretty easy. I am working with 1 16X (100 inst) loop as in hardware UARTs. Ocassionaly this might short cycle the background loop (if all 4 ins, end a byte on the same cycle, the background loop won't get much time). But this can only happen a maximum of once every 160 cycles so shouldn't be a problem. Tom. ----- Original Message ----- From: Stephen Holland > Subject: Re: [Serial I\O (was Re: TMR0 Latency]] > Anytime the RTCC register is written to, the prescaler register (internal - > not the prescaler ratio) is cleared. > BTW, the 2 additional 16-bit timers and larger RAM (262 bytes) of the > SX48/52 might help your application. > Stephen