Paul (and Jason), without knowing the details of the process and the
`floor plan' of the chip, I can only speculate. RB4..7 have additional logic
for the interrupt-on-change feature as well as RB0 for external interrupts.
RA has analog and timer inputs. RC has many functions and RD and RE are
normally used for a standard parallel bus interface. I really wish they
would have used RA5 but they would probably have to sacrifice an A/D channel
and the slave-select input for the MSSP module. Obviously they had to trade
something for the capability. It would be nice if they had moved LVP to one
of the spare pins in the PLCC and QFP packages.

   - Tom

At 07:58 AM 10/24/99 +1000, Paul B. Webster wrote:
>Jason Muhammad wrote:
>
>> I do not know why Microchip would stick the Programming pin (RB3) in
>> the middle of a port (RB0-RB7)...  Why not Bit7 of a port so you would
>> read/write 0x00-0x7F?
>...
>> Less confusing.  What do you think?
>
>  I think it's a right foul-up!  As I see it, LVP is basically un-usable
>and you need to use a 12V programmer and *always* disable it.
>
>  Otrherwise regard PortB as a second PortA - incomplete, unsuitable for
>parallel byte-wise transfer.
>
>  It appears to be a truly amazing extension of their design psychosis;
>like saying you shouldn't use OPTION and TRIS instructions which *are*
>still perfectly valid on this processor but won't work on the only truly
>byte-wide port remaining, where you probably most *NEED* to use TRIS!
>
>  (Or will it?)


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)