Yes,it is possible. The best way is to use an external oscillator with
sufficient drive and then route the output to all of the OSCIN pins on the
PICs (I forget which pin this is,but it's in the datasheet). I think you
also want to put the PIC in HS mode (again, going from memory, it might be
XT).

A thought occured to me about the synchronization: Commands like BSF and
BCF should always output to the port pins on the same cycle,right(I think
its Q4)? Why not make a piece of hardware which sends the clock to several
PICs simultaneously. However, to sync them, it runs the clock very slow and
withholds the clock from all but one PIC at a time. Each PIC is programmed
with several BSF and BCF commands. The clock hardware would feed the clock
to each PIC individually until it saw a rising edge (BSF) on an output pin.
It would then go to the next PIC, do the same. Then, you would have all the
PICs at the same Q phase,and you could simultaneously feed the normal fast
clock,and the special clock gen could be turned off. The special clock
circuit could even be a PIC itself.

Can anyone see any problems with it?

Sean

At 11:26 AM 10/14/99 +1000, you wrote:
>Is it possible to run multiple PIC's of one oscillator source. I don't want
>them synced or anything (I know the Q cycles will be out), it's a board
>space and (possibly) a calibration issue. Have a project that will prob.
>require multiple PIC's. Be much nicer to have 1 oscillator. Ideally it
>wouldn't matter how many PIC's were hooked up (but this may not be possible
>with reasonable accuracy due to load). The other advantage of this is a
>single clock calibration routine. If calibration was an issue then all chips
>should be able to be calibrated simultaneously (assuming the design kept the
>clock equal at all PICs), thus if the calibration were off slightly it
>should be off for all PICs and there shouldn't be drift between PICs
>(although I don't need to count on this and wouldn't unless absolutely
>neccesary).
>
>I must say, a Q cycle synchronisation capability would be a fantastic
>addition for multi PIC projects. Something like the synchronisation scheme
>used in multimaster I2C (from memory) to obtain clock sync. The basic idea
>of this would be a Clock hold pin on your PIC's. If this pin were held low
>the PIC would not be able to rollover from Q4 to Q1, hence you would tie
>this pin of your PIC's together, hold it low for a few cycles (after OSC
>startup) to get all the PIC's at the Q4->Q1 transition, then let it go high,
>this would cause all PIC's to start at Q1 at the same time. Of course this
>relies on all PIC's having identical clocks (have to be careful of rise\fall
>times due to capacitances etc), and prob. wouldn't be exactly rock solid.
>But If you could hold them steady for a few million cycles between resync's
>it would allow extremely fast (theoretically at the clock rate) data
>transfers with no physical synchronisation. Ideally you could set up the
>hardware to, do automatic synching (e.g. every X million cycles, do a 4
>cycle sync). Don;t know if it'd work in practice but I like it in theory.
>
>Tom.
>
|
| Sean Breheny
| Amateur Radio Callsign: KA3YXM
| Electrical Engineering Student
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