At 09:40 23/09/99 +1000, you wrote: >Unfortunately I don't want large quantities and they ain't cheap in small >quantities. > >A FPGA based solution was something I had considered. A small FPGA could >handle 8 or even 16 rotary encoders and memory map their values. This ould >be one way to go but an FPGA would cost about as much as my ADC and the >rotary enc's would cost about AU$100-200 more. Also, I have no FPGA >experience. > >I was more reffering to using the PIC to decode them when they were >multiplexed with other functions would be hard. However I haven't looked at >the pulse width of the average rotary enc. so a Scenix might be able to poll >them fast enough. It's still less expandable than a knob based solution and >that's my major worry. A 8 channel ADC becomes 15 channel with one AU$1 >4053. It costs about AU$160 to upgrade a 8 rotary enc. box to 16. > >Thanks anyway, >Tom. >----- Original Message ----- >From: Dennis Plunkett >Subject: Re: A/D Challenge >> I have not been watching this tread much, so my comments may be of little >> use. But it seems that a rotary encoder (Cheep to make in large >quantities, >> just look at a mouse, it has two!) can be multiplexed, as you are only >> looking for a change in state of sine, then you look at the cosine to see >> which way it is going. This can be done with simple logic, you will have >to >> poll at a pre determined rate applicable to the maimum rate of change *2 * >> number of ports. >> You can take this one setp further and put this into a simple FPGA, thne >> just reas out the real values. >> >> Dennis > > Yep a pot soultion is cheep and simple, I see that people are starting to bog you down with anti aliasing stuff etc. This can make a simple task quite hard indeed. Lets get back to basics:- 1/ How many pots? 16? 2/ How many steps 64? 3/ Reaction time 300mS? The number of POTS will control the base sample speed The number of steps controls the accuracy and the aquisition rate Reaction time will control the variation of the base sample speed To sample a change of state in 300mS over 16 POTS, you will need to sample all pots within the 300mS period. Thus the ADC must settle and read within 300/16 (mS) = 18.75mS (Slow enough for a Sigma delta at slightly better than 53Hz. The rest comes down to a low pass filter which must have a time constant of 1/10th the sample time/5 to have little effect or something like an 8k2 into a 4n7, a buffer may be used to then drive the ADC, but should't be a problem. This sort of Sigma Delta converter can be created cheaply (See M/Chip app note) and 6 bits is all you need (7 will be no problems). As this is connected to a system that can greatly change in value over the sample period, I would suggest that you look at a simple sample and hold circuit. This can be a simple unconnected port on a spare channel on the mux (Wait for the comments on that, but if it is on a good Ground plane, infliced noise is minimal, also note that a bleed resistor would have to be over 100meg not to have an effect) that is switched to after the read cap is charged. So all this can be yours, for the cost of a PIC, current source (Transistor a couple of diodes and a resistor), OPAMP, compator (Don't use an OPAMP for this) and a handful of resistors and capacitors. You will also need 3 by 4053 to do the 16 inputs and control the converter. Dennis Dennis