Thanks for all the help and suggestions from everybody. Sorry my 'input'
has been so long in coming, but I have been overwhelmed with things to
do which were not remotely connected to electronics. Here, however, is
my 'feedback' on some of the suggestions to correct my problem (I
haven't had a chance to actually implemented any suggestions yet). I
apologise for the mass reply, as it is aesthetically unpleasing and
quite possibly distasteful, but the most efficient for this situation
(that is, if anyone is still paying attention to this thread).

Lance
The source impedance is a little of an unknown for me. The 'on'
resistance of the multiplexer is at worst 200 Ohm. That is in series
with the pots which are 10kOhm. The unknown is the resistance of the
voltage regulator I am using (7805 by JRC). However, since this is in
series with one branch of the pot, its affect *should* be minimal. Since
the specs indicate that the input resistance to the the A/D should be
less than 10kOhm, placing buffers at the A/D inputs could have a
substantial effect. Depending on how any software hack works, I may try
this. Anyone have any recommendations about for a package with 3 or 5
op-amps?

Brent
I had actually implemented the first version of hysterisis you
mentioned. The problem was that depending on the first sample, the
values would be limited to even or odd values (basically the sampling
rate was such that every 7 bit A/D value was recognised). Since the pots
are being constantly sampled it took violent tweaks to move from odd to
even or vice versa. Of course, the hysterisis was implemented on the 7
bit value, but I'm not so sure it would make a difference with 8 bits.
The second version of hysterisis you mentioned had not crossed my mind.
It seemed like a revelation. Then I realized that that method
effectively eliminates the rails (i.e. if at 125, one would get to 126
by rotating to 127, but from 126, there would be no way get to 127).
Regardless, I am going to implement this and either turn off the
hysterisis near the rail, or substitute it with some other algorithm
(yet to be determined) at the rails.

Robert
The 16c7X use successive approximation for the A/D algorithm, and
although I'm not positive, I believe this is implemented from MSb to
LSb. If this is the case (does anyone know for sure one way or the
other?), then the noise on the LSb+1 bit to the LSb would be
'independent' as far as I could tell (in truth, the noise would
obviously be related, but to determine how would be a project in and of
itself).

William/bowman
I considered averaging, but the minimum required 4*40=160 data registers
(200 if a total one was used for each pot) are simply not available on
my selected device (16c73a -> 2 banks of 96 = 192) given all the other
things I have in memory. I may try averaging only two samples since this
would only require 1 or 2 data registers per pot depending on
implementation. As for taking several samples in succession for each
pot, I simply cannot clock at a speed fast enough (I am already at the
proper maximum 20 MHz) for 'real' time operation if this is implemented.

Morgan
Your hysterisis suggestion is similar to Lance's suggestions, and what I
plan on implementing first. I have not had a chance to look at the
archive, so I do not know yet what the MOMA filter is (I have joined the
list relatively recently), but hopefully I will get a chance before I
have to decide on anything permanently.

Harold
I am genuinely glad to hear that you have your project working (this
gives me great hope in terms of not having to go to an off chip A/D).
May I ask what values you use for your bypass capacitors and what type
of voltage source you are using?

Thomas/Jeff/Bo
I would be interested in hearing how your project works out with the
encoders. I had thought of using encoders, but opted for the A/D
approach because of both pin count and associated cost. Have you had any
luck in locating 128 position encoders in your stated $10 (AU?) price
range.

Paul
4000 instructions is definitely enough, if several pots are not changing
simultaneously. In that case, one would either have to wait for the
transmitter (which chews a lot of time if several values are to be sent
- especially if bit banging is used), or stagger the sampling of the
pins so that as few encoders as possible finish at the same time.

ADC Suggestions
Thank you for the off chip A/D suggestions, but given all the other
suggestions, I will stick it out with the PIC A/D until I have exhausted
them since their required added complexity is less that having to
communicate with several added chips.

Once again, thanks to everyone for their input.

Mario

--
If it wasn't for the last minute, nothing would get done.