You could try the DalSemi 2450 quad 1-wire a/d converter, uses only one
pin to communicate and you can hang a bunch of them off of the same bit
and start them converting at the same time and then come back and read
them after the conversions are complete.  This would give you a nice
parallel approach to conversion and the A/D are configurable up to 16
bits.  I just got my samples and I am about to hook them up to my solar
panel charger for my weather station.  I will let you know how they work
in the field.

joe


Mario Thomaidis wrote:
>
> Hello,
>
> I am using a 16c73a to sample an array of 40 pots (10k). The pots are
> passed through an 8 to 1 multiplexer (MM74HC4051, five of them),
> selected by way of three select lines, and are inputted into all five of
> the A/D channels.
>
> Set-up Info
> I am currently allowing for an aquisition time of 20us. Also, while I
> only require 7 bit resolution, I am allowing for conversion for a full 8
> bit value. I have tried both Fosc/32 and RC for the conversion clock
> sourcing (one of my questions). I am also including a 2.5*Tad reset time
> after a conversion before I begin aquiring the next A/D channel. I have
> filter (charge sourcing) capacitors on the pot output pin (20 nF), the
> multiplexer output pin / AD input pin (5 nF) and on Vdd (5 nF and 4.7
> uF).
>
> Problem
> As I indicated, I only need 7 bits of *stable* resolution. The problem
> is that while I allow for full 8 bit conversion and discard the LSb, the
> 7 bit value is unstable (can oscillate between two values). I should
> indicate that the oscillation do not happen to all the pots at the same
> time, only a couple at once (but all of them at some point). I have
> looked through the Microchip literature and the PICList archive, but
> have not found any helpful info. In fact, I have found some
> contradictory (or, at the very least mutually exclusive) information.
>
> Contradictory Info
> For example, in FACT002 Table 1, it indicates that the RC conversion
> clock can be used with any speed clock source (I use a 20 MHz crystal
> clock oscillator), while in the DS30390E Table 13-1, it indicates that
> the RC mode should only be used in sleep mode for devices with clock
> speeds above 1 MHz (to reduce digital switching noise). Personnaly, the
> latter makes more sense to me.
>
> I have even rearranged my code so that no output pins are changed during
> the converion (as per the advice in FACT002). I was sure this was my
> problem ... but just like the cat ...
>
> Does anyone have any insight into what I may be doing wrong. Does anyone
> know of any hardware type of filtering I can do to improve my resolution
> (e.g. better capacitor values)? Or how about some simple code technique
> (e.g. wait longer between samples)? I have considered software
> filtering, but since I would have to run the filter 40 times (once for
> each pot), I have been inclined to avoid it. Unless of course someone
> could direct me to a simple and quick algorithm to do this (I don't mind
> codifying and then posting the code). I am almost at the point of
> turning to an off chip A/D. Has anyone suffered through the same or
> similar problems? Any insight would be greatly appreciated.
>
> Mario