Dennis,

I have used OrCad Express, Capture, and Layout Plus at one time or another
throughout my
electronics career so far.  And, like any software package, there is a
learning curve associated
with it.  I didn't much care for any of OrCad's products when I first
started, but after a while, I got
used to it, and now probably wouldn't change unless I just had to.  My point
is that once you get
to know the package, you can make it do just about anything you want it to.
So the fact that top
down design is not implemented isn't as much of a problem as it may first
seem.  What I mean
to say is that when you first look at a new cad package of any kind, you
easily realize what is
and isn't there and you say to yourself "Boy, why didn't they implement this
or that", but when it
comes down to it, you learn the package, learn it's quarks, figure a
workaround, and start making it
do what you want it to do, regardless of whether it was designed to do
things that way or not.
I hope I've helped you in some way, and not just confused you more, but I do
believe that almost
any cad package can be made to perform nearly anyway you want it to as long
as you study the
package and learn it, then you can use it creatively to perform those
functions you want it to.
Granted, there are exceptions, but I haven't let that stop me.

Okay, I'm done now.  Good luck in your review.  And good luck in your
Masters program.


Regards,


Jim
-----Original Message-----
From: Dennis Plunkett <dennis@RDD.NECA.NEC.COM.AU>
To: PICLIST@MITVMA.MIT.EDU <PICLIST@MITVMA.MIT.EDU>
Date: Wednesday, September 01, 1999 8:07 PM
Subject: Re: [OT] ORCAD EXPRESS


>2/9/'99
>
>
>Hello all,
>Sorry that this is a lot OT but...
>I have to use a software package that I must review for my Masters, and
>well I have not spent much time (Only got 3 hours at it so far)
>
>Last night was the first time that I have used ORCAD EXPRESS (To implement
>an FPGA), and well...
>One thing I did nottice is that you can not perform top down design, it
>requires bottom up. I aslo seen that the design itself in the directory
>structure does not hold the same hierachial format and appears flat,
>including the need to set one of the schematics as the root (No default).
>Errors during compilation for simulation don't point you to the error
>
>On simulation I could not figure out how to activte a word patten generator
>(Does it have one, or do I have to use some text file?)
>
>You can get caught with saving a project vs saving the current work
>
>In general I must admit that I have not given this tool much of my time
>(Did implement and test an 8 to 1 MUX as a hierachial format of 2 to 1 MUX
>to form a 4to1 and simulate it), but first impressions are important and
>the ease of driving and expectations are also important (Perhaps I an a bit
>biased due to me testing software applications on a daily basis)
>
>While other aspects are the same old same'o' which made be fell NEC (Nice
>Easy and Comftable). So I would say (Ignoring all the bugs that I was able
>to create etc (Not listed here)) that this tool is good but has a few
>quirks (But the again so do all the others) and does not seem as
>intergrated as the Altera MAX2 (Just from the FPGA point of view), but then
>again this tool will do ccts and other FPGAS etc.
>
>Do you blokes have any comments that may sway my thoughts, what problems
>have you found with it etc. (Plase don't say that tool X does Y, I have to
>look at this tool on its own)?
>
>Dennis