On Mon, 30 Aug 1999 18:08:15 +0100 Barry Coram writes: > > I have since found out that these static RAM chips have to be set > into a 'data retention mode'. Now can somebody please point me in > the direction of a suitable circuit (simple if possible) which will > reliably set the RAM chip into this mode on power down? It isn't really complicated. The data retention mode is: CS inactive All inputs at full CMOS levels Vdd possibly reduced First, you need to be sure the CS pin stays high (same voltage as Vdd) so the chip is inactive. It's a good idea to set WE high also to reduce the chance of an accidental write. This next part is important. Although the logic states of the other pins (address, data, OE) doesn't matter, they are still live CMOS inputs. If they are not solidy at one logic level or the other (I think the spec is within 0.2V of the Vdd or ground pin), the chip will draw a relatively large current. Usually with the rest of the circuit powered off, it will hold the pins to ground potential. The only major problem is getting CS (and possibly WE) to follow the battery Vdd line. In a slow circuit you could use a resistor. If you need fast access, one of the Dallas or similar chips integrates the switchover from regular to battery power and a fast gate to drive CS and hold it to Vdd when the RAM is on battery power. Also be sure that your RAM is rated for low, low power battery backup operation. Often this means it has two "L"'s in the part number, not just one. Get the manufacturer's data to be sure. ___________________________________________________________________ Get the Internet just the way you want it. Free software, free e-mail, and free Internet access for a month! Try Juno Web: http://dl.www.juno.com/dynoget/tagj.