Like this: ftp://ftp.drzyzgula.org/pub/electronics/adap28-2.jpg ?
Great idea. The board is just about the same surface area, so
there shouldn't be any cost difference. The only problem I
see is that the pin heads under the SOIC will have to
be no thicker than the elevation of the SOIC underbelly
from the PCB, which would seriously limit the choice of
pins. Maybe you meant to put the SOIC all the way outside
the DIP outline?

--Bob

(I suddenly realized I could use the CAM processor to generate
a TIFF file rather than printing to PostScript, and I then
converted to jpg with xv on my Linux machine. It's got some
aliasing problems, but at least it will pop up inline
on a browser).

--Bob

On Tue, Aug 24, 1999 at 08:19:58AM +1000, Paul B. Webster VK2BZC wrote:
> OK, noted the design simplifies if you "cheat" and use 0.7" spacing.
> What happens to the design if you assume a 0.3" "Skinny Dip" pinout.
>
>   Yes, I know it overhangs, but it certainly fits a breadboard (indeed,
> it allows you more "holes" to use).
>
> --
>   Cheers,
>         Paul B.

--
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Bob Drzyzgula                             It's not a problem
bob@drzyzgula.org                until something bad happens
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