For a similar application (driving external SRAM), I used one 8
bit port to drive the data lines of the SRAM AND a bunch of 8 bit
parallel latches.  I also have PIC pinse for -WR, -RD, and a latch line
to each of the latches.  The outputs of the parallel latches drive the
address lines of the SRAM.  I'm also driving an LCD module and an FDC
(for which I STILL have a bunch of code to write!) with the resulting
data and address lines.
        There are also 8 pushbutton switches on this project, which used
to use a lot of I/O pins.  Now I have a string of resistors (using
isolated resistor networks) and the switches select which tap is sent to
a single A/D input on the PIC.  I'm using SPDT switches so "lower
priority" switches are locked out when a higher priority one is pressed.
        Also, on this project, I've got an 8 position DIP switch.  One
side of each switch is connected to the "data bus" (driving the SRAM).
The other side of each switch is connected through a 10K resistor (part
of a network) to +5V (other resistors in the network serve as general
pull-ups).  To read the DIP switch, the PIC is set to output and all
lines driven low.  The PIC is switched to input, then after an
"appropriate" delay, the port is read.  Lines with closed switches will
have gone high while the other lines are still low.
        Lotsa functions... very few pins...

Harold



Harold Hallikainen
harold@hallikainen.com
Hallikainen & Friends, Inc.
See the FCC Rules at http://hallikainen.com/FccRules and comments filed
in LPFM proceeding at http://hallikainen.com/lpfm


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