At 09:23 19/08/99 -0600, you wrote:
>Probably do it in a FPGA rather than a CPLD.  Large FIFO's eat up CLB's in
>them, but there are a few that have ram blocks (like Xilinx spartan series),
>and when Phillips was here touting the CoolRunner, I talked with the
>designer of the next generation and she was saying they were going to put
>RAM blocks as well.  I'm not sure if that part was ever finished, or what
>stage since they were bought out by Xilinx.
>
>


I would not use an FPGA! infact it is too slow to connect to a PCI bus and
performa all the stuff that you may want (Need more infomation before I can
fully clarify that one) You may bee better off with a GA as they are faster
(Try to get an FPGA to do a SONET interface to a PCI bus!) You may have to
hand craft the thingo to get it to work (FPGA) this will introduce another
set of problems.
As for RAM, YEP can do Look at the ProASIC 500K series from Actel, it has
up to 138kbits (A bit on the taki side as they are a new release). But you
will find that all the manufacturers include embedded logic or RAM.

Dennis