On Thu, 12 Aug 1999 15:31:01 +0100, you wrote: >In article <37b29b9e.402375@smtp.netcomuk.co.uk>, Mike Harrison > writes > >>Not directly relevant but I know of at least one other case where the >>bondout chip used in a picmaster probe behaves differently to the >>'real' silicon, so it's not unheard of. > >Mike, out of interest, can you recall the details? Yes - when sending synchronous data (can't remember if it was the SSP or SPI) in master mode, instead of a nice regular group of 8 clock pulses, 'gaps' appear in the clock pulse train on the emulator, but not on the real device. The pattern of gaps depended on something - can't remember if it was the data pattern or something more obscure. You still get the right number of clock pulses, and the data comes out at the right time, so you won't notice this unless speed is critical, or you're doing what I was trying - using the sync data output to generate pulse patterns.