>There was debate over whether strange things happen when INDF is used to
>access RAM banks 2 & 3 in the 16C76/77. It was suggested that it was
>necessary to always set/clear RP1 together with IRP in order for INDF
>accesses to work correctly. However it would fail only when certain
>(unrelated) operations involving the STATUS register occurred.
>
>This is not IMHO how it should work, and I can find no reference to a
>bug in Mchip documentation.
>
>My own experience is that this is true for my emulator (RICE16) but
>probably not for the "real" part. Of course this is still bad news!
>
>Does anyone know the truth of the matter?

We are shipping a product which controls IRP separately from INDF in a '76.

It works fine in our product.

Andy

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Andy Kunz               Life is what we do to prepare for Eternity
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