Justin, depending on speed, you might want to consider a CPLD. I have a
lot of experience with Lattice Semiconductor.

   The Lattice ispLSI1016E-100LJ is a 100MHz 44-pin PLCC device. It costs
around $6-$7 in single quantity. It's hard to explain the device's resources
without having studied the architecture. It includes:

        32 I/Os
         4 Dedicated Inputs
         3 Clock Inputs
         1 Global Reset shared with one of the clock Inputs
         1 Global Output-Enable shared with one of the Dedicated Inputs
      2000 Gates
        96 Registers
        16 Generic Logic Blocks (GLB)

   Again, there is more to it. Those resources are arranged in GLBs or
Generic Logic Blocks. They include several options such as hardware XOR
gates, OR gates, product term Resets, Output-Enables, and Clocks. Each GLB
includes 4 registers which can be configured in several ways. There is also
a `High Speed Bypass" option to route product term outputs directly to the
output macrocells. Output macrocells can be configured in a variety of ways
such as Inputs, Outputs, Latched Input, Bi-Directional with or without
Latched Inputs, and 3-State.

   Lattice currently provides the ispExpert software with a free six month
license. This is an update to the Synario package which Lattice acquired. It
provides schematic and ABEL-HDL entry. Also included is a gate-level
functional and timing simulator. There is a lot more to the package but it's
very easy to use. It supports most of their devices as well as generic GALs.

   Programming is trivial with just a 5V supply. The Lattice software to do
this is free. The download cable uses a 74HC/LS367 and a few passives and
connects to a PC parallel port. Most folks already have the parts in their
`stash'.

   To build the Lattice download cable, see my web page at:

      http://www.teleport.com/~thandley/Wilbure.htm

   For more information about Lattice Semiconductor's products and to
download the ispExpert design software, contact:

      http://www.latticesemi.com

   - Tom

On Wed, Aug 04, 1999 at 07:17:50PM +0800, Justin Grimm wrote:
> Hi all
> Ive got a circuit design that uses 4 or 5 TTL chips to take in
> 16 address lines to enable various peripherals.
> Im looking to reduce the IC count to 1 chip.
> Ive heard about pal,gal and pld chips but have no idea how
> to use them or program them. Would these chips suit the job
> and if so where do I learn about them?


------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)