On Tue, 29 Jun 1999 10:49:40 -0700, Mark Willis wrote:

>Dan Larson wrote:
>>
>> On Tue, 29 Jun 1999 09:37:38 -0700, Mark Willis wrote:
>>
>> Depends on how low Vss is <BG>
>
>  Don't think so, !TO bit wouldn't make sense otherwise!  Quoth the F84
>docs,
>

Oh, I was hoping to get a chuckle at the expense of the poor
PIC that has gone crazy because the supply voltage is too low.
IIRC, The 18F84's don't have BOR yet..

>[ Power-up Timer (PWRT), which provides a
>[ fixed delay of 72 ms (nominal) on power-up only. This
>[ design keeps the device in reset while the power supply
>[ stabilizes.
>
>  Note the "Keeps the device IN RESET" there.  Sure, once that 72 ms is
>over, the code'll start running, but not UNTIL then!  <G>

But, what is the timing of the trailing edge of reset in relation to
the Q cycle?   Will execution begin on the first Q1 after reset goes high
while transient Q2,Q3, and Q4's might pass before the next Q1, depending on
the timing of MCLR, OR, will reset actually make the internal clock reset the
Q cycle to Q1? IOW, is the Q cycle synchronous with a free-running Q counter,
or synchronous with the MCLR trailing edge?



I never *thought* code could run while in reset.  A failed attempt at
some subtle humor backfired on me here twice with this!  If it were
true it would be the answer to all computing speed problems since
any number of instructions executed while in reset greater than
zero would result in an instruction per clock cycle ratio of infinity!

>
>  Manual example - Think of two pics run at 1 Hz.  Stop the clock to the
>first one that raises RB7 high, until the other PIC also raises RB7,
>then let both continue - they're synchronized.  Proper gating should let
>them do this at far faster clock speeds than 1 Hz, of course.  I'll do
>that later though, have an appointment today <G>
>

I'd really like to see the results of something like this.  I've thought
of doing it before with chains of processors in robot appendages.

>> >  (Does someone else's software run while the startup timer's running?
>> >Evil Minds want to know <G>  How do they DO that?)
>> >
>>
>> If it is on someone else's PIC, it does!
>
>  How does anyone's software run while the PIC's held in reset?  Hmmm...
>

If the PIC in reset is not the PIC on which the software is running <G>.

I'll stop trying to be funny now.  I have made a disaster out of this.

But seriously, I'd really like to know for sure if Q cycle sync can
really be done.  The parallel processing potential is interesting.

Dan