If the input clock is very intermitent skipping cycles, you can not
trust it to teach your software pll how long is a real pulse.  Well, it
is possible if your software select the shortest timming received in a
sequence during 1 second or more. Then the software pll should keep
counting time to generate the 90 degrees delay, what is good, since it
can decide if the clock output can be triggered by the incomming clock
or by its timeout routine.  If the timeout happens and right after that
comes the incomming clock (time slide), the 90 degrees delay would be
able to trigger the output signal by the incomming clock rather than the
timeout routine, so the timeout routine could be resync.  The 90 degrees
is just generated by timeout for a complete pulse divided by 4.

Running the microcontroller at 12MHz, the software pll has only 500
clock pulses to count a 24kHz incomming clock, and it means its
resolution would be 1/500 or an accuracy of 0.2%.

Wagner.

varney wrote:
>
>     I need an output clock at about 22.73 khz running at 90 degrees phase
> lag to an input clock. The input clock is also 22.73 Khz and may drift by 1
> khz.  The input is very intermittent and will skip cycles a lot. The output
> may not skip cycles and must sync with the input when available.
>
> Otherwise known as a software PLL.
>
>     I have working code that will do this. however it is very clumsy and I
> am not sure how accurate. If someone is interested in looking at my code,
> let me know and I will send it. I did not publish it with this e-mail due to
> length.
>     There may be nothing wrong with my code, but the more accurate, faster
> and smaller the better.
>
> Part number 16F84  @ 10 Mhz but will be upgraded to the 16F873  @ 20 Mhz
> when available.
>
> Gordon Varney